In space-based environments, ionic strikes by sub-atomic cosmic particles are known to introduce circuit disturbances in digital integrated circuits. These circuit disturbances are known as upsets or single event effects (SEE) and can be generally classified into three types: single event upsets (SEU), single event data path transients (Data SET), and single event transients of the clock distribution (Clock SET). These three types of SEEs are traditionally managed using different approaches. In conventional systems, stored logic values are typically protected from SEUs by using three storage elements, such as registers, to store redundant copies of the data. A majority voter is then used to output the correct data value, even if one of the storage elements gets corrupted. The use of the majority voter protects against an upset affecting any one of the three storage elements. However, if an upset strikes a data path, erroneous data from the data path may be stored in all three registers, thereby making the use of the majority voter futile. Further, if an upset strikes a clock signal, stored data or logic states may be inadvertently clocked and corrupted.
Existing methods to mitigate data SETs and clock SETs are applied independently. For instance, data SETs are typically mitigated by adding logic on the redundant register data inputs to filter any upsets that may affect the data path. However, the logic used for filtering these upsets must be set for a particular maximum upset pulse width. The logic used for the filter will vary with variations in process, voltage and temperature (PVT) conditions, causing either incomplete filtering or the need to set the filter for larger than desired pulse widths to compensate for variations in the PVT conditions. Filtering larger than necessary pulse widths adversely affects circuit performance and is therefore, undesirable. Moreover, these techniques do not mitigate Clock SETs.
Conventional techniques for mitigating Clock SETs include creating a custom clock splitter that incorporates logic to filter radiation upset pulses before passing the clock signal to a register. However, the clock-splitter structure is unique to a particular clock architecture and is not easily hosted on, or ported to various digital integrated circuit designs as it requires a non-standard, custom, cell design. Further, as a single pair of clock phases is fed to the storage elements, there remains some common output circuitry that may be subject to upsets and be affected by a clock SET at the storage elements.
It is with respect to these considerations and others that the disclosure made herein is presented.